Generally, offset voltages may be introduced into a circuit as a result of component variations arising from non-ideal manufacturing processes. Such offset voltages may affect normal circuit operation. Thus, there is a need to cancel or compensate for offset voltages.
In a more specific example, some integrated circuit technologies (e.g., complementary metal-oxide-semiconductor (CMOS)) suffer from offset. In a perfect system, transistors are perfectly matched and the same voltage applied at the gate of each transistor causes the transistor to switch identically. Put another way, perfect transistors in an integrated circuit have the same switching voltage. However, in the real world each transistor has slight differences. Offset can be modeled as a voltage at the gate of a transistor, and the voltage could be different between transistors. Circuit designs which rely upon matched transistors (e.g., CMOS analog to digital converters (ADC)) often attempt to compensate for this by performing offset cancellation.
A number of offset cancellation techniques exist but these existing techniques have drawbacks associated with them. Some techniques have a size penalty because required components are larger than desired and/or are not the smallest such component. More specifically, some solutions require certain types of transistors and these transistors tend to be larger. For high speed application and high integration, it would be desirable to use smaller transistors. Another issue is power consumption. Some offset cancellation techniques consume (DC) power. This is unattractive, especially for these low power applications, such as mobile or portable applications. Other solutions incorporate capacitors, which may slow down the speed at which the system can operate since capacitors may increase the loading of the critical path. It would be desirable if new offset cancellation techniques could be developed which overcome one or more of these obstacles.